Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processor executing programs, such as, communication and multimedia programs. The processing systems for such products include a processor and memory complex for storing instructions and data. Large capacity main memory commonly has slow access times as compared to the processor cycle time. As a consequence, the memory complex is conventionally organized in a hierarchy based on capacity and performance of cache memories, with the highest performance and lowest capacity cache located closest to the processor. Data and instruction caches may be separate or unified or a combination of separate and unified. For example, a level 1 instruction cache and a level 1 data cache would generally be directly coupled to the processor. While a level 2 unified cache may be coupled to the level 1 (L1) instruction and data caches. Further, a system memory is generally coupled to the level 2 (L2) unified cache. Coupling to external storage such as flash memory, hard disk drives, optical drives, and the like may also be provided.
The level 1 instruction cache commonly operates at the processor speed and the level 2 unified cache operates slower than the level 1 cache, but has a faster access time than that of the system memory. Alternative memory organizations abound, for example, memory hierarchies having a level 3 cache in addition to an L1 and an L2 cache. Another memory organization may use only a level 1 cache and a system memory.
One of the principles behind why a memory hierarchy for instruction caches can be used is that instructions tend to be accessed from sequential locations in memory. By having caches hold the most recently used sections of code, processors may execute at a higher performance level. Since programs also contain branch, call, and return type instructions, and support other non-sequential operations such as interrupts, the principle of sequential locality may be maintained only for relatively short sections of code. Due to such non-sequential operations, an instruction fetch to an instruction cache may miss, causing the instruction fetch to be applied to the next higher memory level that operates with a higher memory capacity and slower access time. A miss may cause the processor to stall awaiting the instruction. In order to keep processor performance high, cache miss rates should be low.
When an interrupt occurs, there is a latency between the time the interrupt event is detected and the time when instructions at the location of the associated interrupt handler have been fetched and can begin execution. The latency may be due in part to the interrupt handler not being resident in the instruction cache resulting in lengthy miss and fetch operations to retrieve the instructions before the interrupt handler may execute thereby reducing processor performance. One approach to reducing the latency includes locking the interrupt handlers in the instruction cache, but this approach effectively reduces the size of the cache, which may further reduce processor performance.